The present invention relates to semiconductor device manufacturing and packaging and more particularly to delamination-resistant array type packages and their method of manufacture.
One type of known semiconductor package includes a multi-layer circuit board comprising a core and one or more dielectric layers, conducting layers and pads. A semiconductor die may be flip-chip connected to external conductive layers of the board with solder balls. Vias (small openings) are made in the dielectric layers to allow conductive connections between layers and typically comprise two pads on different layers of the board that are electrically connected by a drilled hole. The hole is made conducting by electroplating or by it lining with a conducting tube or a rivet. A so-called “plated through hole” (PTH) typically provides vertical connections through the core to the conductive layers of the circuit board. Plated through holes are drilled using lasers or a mechanical drill.
A known array type manufacture of multiple devices is used on BGA (Ball Grid Array) packages where a plurality of dies is disposed on a substrate in the arrangement of a matrix array. The substrate may be a copper clad glass fiber laminate. The dies are connected to signal terminals of the substrate by wirebonds and then the dies are encapsulated in a protective coating using a molding process. In the molding process, a plurality of substrates with the dies is placed between upper and lower molds. When the upper and lower molds are combined, gaps between the two molds and the die substrates are reserved as runners and gates. Colloidal particles are placed at the center of the mold which are subsequently melted to produce a compound flow which is injected into the mold cavities through the runners and gates so as to cover the dies. FIG. 1 shows two die substrates 100 (in plan view) on completion of the molding process. FIG. 2 shows an end view of the substrates and dies. Sealing compound regions 101 (covering the individual dies), runner regions 102, mold gate regions 103, and a residue 104 are formed after the compound flow is cured. The runner regions 102, the mold gates 103 and the residue 104 comprise a cull which needs to be stripped by a degating process. In a typical degating process, a plunger exerts a force on the residue 104 which results in the cull breaking away. A problem of the degating process is delamination of the substrate at the regions of the mold gates 103. For instance, an outer copper layer of the substrate may stick to the mold gate region and peel way on degating, leaving fibers of the substrate exposed. Delamination can even occur when the mold gate region of the substrate has been gold plated in an attempt to aid mold gate release. Delamination is undesirable as it can lead to moisture ingress into the package with a resulting degradation of performance or even failure of the packaged semiconductor device.
Thus it would be advantageous to provide a package which is less susceptible to delamination on degating.